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this document is a general product descripti on and is subject to change without notice. hynix semiconductor does not assume any responsibility for use of circuits described. no pat ent licenses are implied. rev. 1.0 / apr. 2005 1 240pin ddr2 sdram unbuffered dimms based on 512 mb 1st ver. this hynix unbuffered dual in-line memory module(dimm) series consists of 512mb 1st ver. ddr2 sdrams in fine ball grid array(fbga) packages on a 240pin glass-epoxy substrate. this hynix 512mb 1st ver. based ddr2 unbuffered dimm series provide a high performance 8 byte interface in 133.35mm width form factor of industry standard. it is suitable for easy interchange and addition. features ordering information part name density organization # of drams # of ranks materials ecc hymp532u646-e3/c4 256mb 32mx64 4 1 leaded none hymp564u648-e3/c4 512mb 64mx64 8 1 leaded none hymp564u728-e3/c4 512mb 64mx72 9 1 leaded ecc hymp512u648-e3/c4 1gb 128mx64 16 2 leaded none hymp512u728-e3/c4 1gb 128mx72 18 2 leaded ecc hymp532u64p6-e3/c4 256mb 32mx64 4 1 lead free none hymp564u64p8-e3/c4 512mb 64mx64 8 1 lead free none hymp564u72p8-e3/c4 512mb 64mx72 9 1 lead free ecc hymp512u64p8-e3/c4 1gb 128mx64 16 2 lead free none hymp512u72p8-e3/c4 1gb 128mx72 18 2 lead free ecc ? jedec standard double data rate2 synchrnous drams (ddr2 sdrams) with 1.8v +/- 0.1v power supply ? all inputs and outputs are compatible with sstl_1.8 interface ?4 bank architecture ?posted cas ? programmable cas latency 3 , 4 , 5 ? ocd (off-chip driver impedance adjustment) ? odt (on-die termination) ? fully differential clock operations (ck & ck ) ? programmable burst length 4 / 8 with both sequen- tial and interleave mode ? auto refresh and self refresh supported ? 8192 refresh cycles / 64ms ? serial presence detect with eeprom ? ddr2 sdram package: 60ball fbga(64mx8), 84ball fbga(32mx16) ? 133.35 x 30.00 mm form factor ? lead-free products are rohs compliant
rev. 1.0 / apr. 2005 2 1 240pin ddr2 sdram unbuffered dimms speed grade & key parameters address table input/output functional description e3 (ddr2-400) c4 (ddr2-533) unit speed @cl3 400 400 mbps speed @cl4 400 533 mbps speed @cl5 - - mbps cl-trcd-trp 3-3-3 4-4-4 tck density organization ranks sdrams # of drams # of row/bank/column address refresh method 256mb 32m x 64 1 32mb x 16 4 13(a0~a12)/2(ba0~ba1)/10(a0~a9) 8k / 64ms 512mb 64m x 64 1 64mb x 8 8 13(a0~a12)/2(ba0~ba1)/10(a0~a9) 8k / 64ms 512mb 64m x 72 1 64mb x 8 9 13(a0~a12)/2(ba0~ba1)/10(a0~a9) 8k / 64ms 1gb 128m x 64 2 64mb x 8 16 14(a0~a13)/2(ba0~ba1)/10(a0~a9) 8k / 64ms 1gb 128m x 72 2 64mb x 8 18 14(a0~a13)/2(ba0~ba1)/10(a0~a9) 8k / 64ms symbol type polarity pin description ck[2:0], ck [2:0] sstl differential crossing ck andk /ck are dirrerential clock inputs. all the ddr2 sdram addr/cntl inputs are sam- pled on the crossing of positive edge of ck and negative edge of /ck. output(read) data is reference to the crossing of ck and /ck (both directions of crossing) cke[1:0] sstl active high activates the ddr2 sdram ck signal when high and deactivates the ck signal when low. by deactivating the clocks, cke low initiates the power down mode or the self refresh mode. s [1:0] sstl active low enables the associated ddr2 sdram command decoder when low and disables the com- mand decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. rank 0 is selected by s 0; rank 1 is selected by s 1 ras , cas , we sstl active low /ras,/cas and /we(along wi th s) define the command being entered. odt[1:0] sstl active high asserts on-die termination for dq, dm, dqs and dqs signals if enabled via the ddr2 sdram mode register. vref supply reference voltage for sstl18 inputs v ddq supply power supplies for the ddr2 sdram output buffers to provide improved noise immunity. for all current ddr2 unbuffered dimm designs, v ddq shares the same power plane as v dd pins. ba[1:0] sstl - selects which ddr2 sdram internal bank of four is activated.
rev. 1.0 / apr. 2005 3 1 240pin ddr2 sdram unbuffered dimms pin configuration symbol type polarity pin description a[9:0], a10/ap, a[13:11] sstl - during a bank activate command cycle, address input difines the row address(ra0~ra15) during a read or write command cycle, addr ess input defines the column address when sampled at the cross point of the rising edge of ck and falling edge of ck . in addition to the column address, ap is used to invoke au toprecharge operation at the end of the burst read or write cycle. if ap is high., autoprecharge is selected and ba0-ban defines the bank to be precharged. if ap is low, autoprecha rge is disabled. during a precharge command cycle., ap is used in conjunction with ba0-ban to control which bank(s) to precharge. if ap is high, all banks will be precharged regardless of the state of ba0-ban inputs. if ap is low, then ba0-ban are used to define which bank to precharge. dq[63:0], cb[7:0] sstl - data and check bit input/output pins. dm[8:0] sstl active high dm is an input mask signal for write data. in put data is masked when dm is sampled high coincident with that input data during a wr ite access. dm is sampled on both edges of dqs. although dm pins are input only, the dm loading matches the dq and dqs loading. v dd ,v ss supply power and ground for the ddr2 sdram input buffers, and core logic. v dd and v ddq pins are tied to v dd /v ddq planes on these modules. dqs[8:0], dqs [8:0] sstl differential crossing data strobe for input and output data. for rawcards using x16 organized drams, dq0~7 connect to the ldqs pin of the drams and dq8~15 connect to the udqs pin of the dram sa[2:0] - these signals are tied at the system planar to either v ss or v dd to configure the serial spd eeprom. sda - this is a bidirectional pin used to transfer data into or out of the spd eeprom. a resister must be connected to v dd to act as a pull up. scl - this signal is used to clock data into and out of the spd eeprom. a resistor may be con- nected from scl to v dd to act as a pull up on the system board. vddspd supply power supply for spd eeprom. this supply is separate from the vdd/vddq power plane. eeprom supply is operab le from 1.7v to 3.6v. 1 pin front side 64 pin 65 pin 120 pin 121 pin back side 184 pin 185 pin 240 pin
rev. 1.0 / apr. 2005 4 1 240pin ddr2 sdram unbuffered dimms pin assignment notes : 1. the test pin is reserved for bus analysis tools and is not connected on standard memory module products(dimms). 2. nc pins should not be connected to anything, including bussing within the nc group. pin name pin name pin name pin name pin name pin name 1 vref 41 vss 81 dq33 121 vss 161 nc(cb4)* 201 vss 2 vss 42 nc(cb0)* 82 vss 122 dq4 162 nc(cb5)* 202 dm4 3 dq0 43 nc(cb1)* 83 dqs 4 123 dq5 163 vss 203 nc 4 dq1 44 vss 84 dqs4 124 vss 164 nc(dm8)* 204 vss 5vss45nc(dqs 8)* 85 vss 125 dm0 165 nc 205 dq38 6dqs 0 46 nc(dqs8)* 86 dq34 126 nc 166 vss 206 dq39 7 dqs0 47 vss 87 dq35 127 vss 167 nc(cb6)* 207 vss 8 vss 48 nc(cb2)* 88 vss 128 dq6 168 nc(cb7)* 208 dq44 9 dq2 49 nc(cb3)* 89 dq40 129 dq7 169 vss 209 dq45 10 dq3 50 vss 90 dq41 130 vss 170 vddq 210 vss 11 vss 51 vddq 91 vss 131 dq12 171 cke1 211 dm5 12 dq8 52 cke0 92 dqs 5 132 dq13 172 vdd 212 nc 13 dq9 53 vdd 93 dqs5 133 vss 173 a15 213 vss 14 vss 54 ba2 94 vss 134 dm1 174 a14 214 dq46 15 dqs 1 55 nc 95 dq42 135 nc 175 vddq 215 dq47 16 dqs1 56 vddq 96 dq43 136 vss 176 a12 216 vss 17 vss 57 a11 97 vss 137 ck1 177 a9 217 dq52 18 nc 58 a7 98 dq48 138 ck 1 178 vdd 218 dq53 19 nc 59 vdd 99 dq49 139 vss 179 a8 219 vss 20 vss 60 a5 100 vss 140 dq14 180 a6 220 ck2 21 dq10 61 a4 101 sa2 141 dq15 181 vddq 221 ck 2 22 dq11 62 vddq 102 nc,test 1 142 vss 182 a3 222 vss 23 vss 63 a2 103 vss 143 dq20 183 a1 223 dm6 24 dq16 64 vdd 104 dqs 6 144 dq21 184 vdd 224 nc 25 dq17 65 vss 105 dqs6 145 vss 185 ck0 225 vss 26 vss 66 vss 106 vss 146 dm2 186 ck 0 226 dq54 27 dqs 2 67 vdd 107 dq50 147 nc 187 vdd 227 dq55 28 dqs2 68 nc 108 dq51 148 vss 188 a0 228 vss 29 vss 69 vdd 109 vss 149 dq22 189 vdd 229 dq60 30 dq18 70 a10/ap 110 dq56 150 dq23 190 ba1 230 dq61 31 dq19 71 ba0 111 dq57 151 vss 191 vddq 231 vss 32 vss 72 vddq 112 vss 152 dq28 192 ras 232 dm7 33 dq24 73 we 113 dqs 7 153 dq29 193 s 0 233 nc 34 dq25 74 cas 114 dqs7 154 vss 194 vddq 234 vss 35 vss 75 vddq 115 vss 155 dm3 195 odt0 235 dq62 36 dqs 376 s 1 116 dq58 156 nc 196 a13 236 dq63 37 dqs3 77 odt1 117 dq59 157 vss 197 vdd 237 vss 38 vss 78 vddq 118 vss 158 dq30 198 vss 238 vddspd 39 dq26 79 vss 119 sda 159 dq31 199 dq36 239 sa0 40 dq27 80 dq32 120 scl 160 vss 200 dq37 240 sa1 * the pin names in parenthesises are applied to dimm with ecc only. * nc=no connect
rev. 1.0 / apr. 2005 5 1 240pin ddr2 sdram unbuffered dimms functional block diagram 256mb(32mbx64) : hymp532u64[p]6 /s0 /dqs0 dm 0 dqs 0 d0 dq 0 i/ o 0 dq 1 i/ o 1 dq 2 i/ o 2 dq 3 i/ o 3 dq 4 i/ o 4 dq 5 i/ o 5 dq 6 i/ o 6 i/ o 7 dq 7 /dqs1 dm 1 dqs 1 dq 8 dq 9 dq 10 dq 11 dq 12 dq 13 dq 14 dq 15 /cs /ldqs ldqs ldm dq 16 dq 17 dq 18 dq 19 dq 20 dq 21 dq 22 dq 23 dq 24 dq 25 dq 26 dq 27 dq 28 dq 29 dq 30 dq 31 /dqs2 dm 2 dqs 2 d1 i/ o 0 i/ o 1 i/ o 2 i/ o 3 i/ o 4 i/ o 5 i/ o 6 i/ o 7 /dqs3 dm 3 dqs 3 /cs /ldqs ldqs ldm /dqs4 dm 4 dqs 4 dq 32 dq 33 dq 34 dq 35 dq 36 dq 37 dq 38 dq 39 /dqs5 dm 5 dqs 5 d2 i/ o 0 i/ o 1 i/ o 2 i/ o 3 i/ o 4 i/ o 5 i/ o 6 i/ o 7 /cs /ldqs ldqs ldm dq 40 dq 41 dq 42 dq 43 dq 44 dq 45 dq 46 dq 47 /dqs7 dm 7 dqs 7 dq 56 dq 57 dq 58 dq 59 dq 60 dq 61 dq 62 dq 63 d3 i/ o 0 i/ o 1 i/ o 2 i/ o 3 i/ o 4 i/ o 5 i/ o 6 i/ o 7 /cs /ldqs ldqs ldm dq 48 dq 49 dq 50 dq 51 dq 52 dq 53 dq 54 dq 55 /dqs6 dm 6 dqs 6 ba 0- ba 1 a0-a13 /ras /cas sdrams d0-d3 cke 0 /we odt 0 i/ o 8 i/ o 9 i/ o 10 i/ o 11 i/ o 12 i/ o 13 i/ o 14 i/ o 15 /udqs udqs udm i/ o 8 i/ o 9 i/ o 10 i/ o 11 i/ o 12 i/ o 13 i/ o 14 i/ o 15 /udqs udqs udm i/ o 8 i/ o 9 i/ o 10 i/ o 11 i/ o 12 i/ o 13 i/ o 14 i/ o 15 /udqs udqs udm i/ o 8 i/ o 9 i/ o 10 i/ o 11 i/ o 12 i/ o 13 i/ o 14 i/ o 15 /udqs udqs udm sdrams d0-d3 sdrams d0-d3 sdrams d0-d3 sdrams d0-d3 sdrams d0-d3 sdrams d0-d3 v dd spd v ref v dd /v ddq v ss serial pd do-d3 do-d3 do-d3 notes: 1. dq,dm,dqs,/dqs resistors : 22 ? +/- 5 %. 2. bax,ax,/ras,/cas,/we resistors : 10 ? +/- 5 %. scl sda a0 a1 wp serial pd scl sa0 sa1 sa2 a1 clock signal loads ck0, /ck0 ck1, /ck1 nc 2 ck2, /ck2 2 clock input sdrams
rev. 1.0 / apr. 2005 6 1 240pin ddr2 sdram unbuffered dimms functional block diagram 512mb(64mbx64) : hymp564u64[p]8 /s0 /dqs0 dm0 dqs0 d0 /cs dqs /dqs dm dq0 i/o 0 dq1 i/o 1 dq2 i/o 2 dq3 i/o 3 dq4 i/o 4 dq5 i/o 5 dq6 i/o 6 i/o 7 dq7 /dqs1 dm1 dqs1 d1 /cs dqs /dqs dm dq8 i/o 0 dq9 i/o 1 dq10 i/o 2 dq11 i/o 3 dq12 i/o 4 dq13 i/o 5 dq14 i/o 6 i/o 7 dq15 /dqs2 dm2 dqs2 d2 /cs dqs /dqs dm dq16 i/o 0 dq17 i/o 1 dq18 i/o 2 dq19 i/o 3 dq20 i/o 4 dq21 i/o 5 dq22 i/o 6 i/o 7 dq23 /dqs3 dm3 dqs3 d3 /cs dqs /dqs dm dq24 i/o 0 dq25 i/o 1 dq26 i/o 2 dq27 i/o 3 dq28 i/o 4 dq29 i/o 5 dq30 i/o 6 i/o 7 dq31 /dqs4 dm4 dqs4 d4 /cs dqs /dqs dm dq32 i/o 0 dq33 i/o 1 dq34 i/o 2 dq35 i/o 3 dq36 i/o 4 dq37 i/o 5 dq38 i/o 6 i/o 7 dq39 /dqs5 dm5 dqs5 d5 /cs dqs /dqs dm dq40 i/o 0 dq41 i/o 1 dq42 i/o 2 dq43 i/o 3 dq44 i/o 4 dq45 i/o 5 dq46 i/o 6 i/o 7 dq47 /dqs6 dm6 dqs6 d6 /cs dqs /dqs dm dq48 i/o 0 dq49 i/o 1 dq50 i/o 2 dq51 i/o 3 dq52 i/o 4 dq53 i/o 5 dq54 i/o 6 i/o 7 dq55 /dqs7 dm7 dqs7 d7 /cs dqs /dqs dm dq56 i/o 0 dq57 i/o 1 dq58 i/o 2 dq59 i/o 3 dq60 i/o 4 dq61 i/o 5 dq62 i/o 6 i/o 7 dq63 v dd spd v ref v dd /v ddq v ss serial pd do-d7 do-d7 do-d7 ba0-ba1 a0-a13 /ras /cas sdrams d0-7 cke0 /we odt0 sdrams d0-7 sdrams d0-7 sdrams d0-7 sdrams d0-7 sdrams d0-7 sdrams d0-7 scl sda a0 a1 wp serial pd scl sa0 sa1 sa2 a1 notes: 1. dq,dm,dqs,/dqs resistors : 22 ? +/- 5 %. 2. bax,ax,/ras,/cas,/we resistors : 5.1 ? +/- 5 %. clock signal loads ck0, /ck0 ck1, /ck1 2 3 ck2, /ck2 3 clock input sdrams
rev. 1.0 / apr. 2005 7 1 240pin ddr2 sdram unbuffered dimms functional block diagram 512mb(64mbx72) : hymp564u72[p]8 /s0 /dqs0 dm0 dqs0 d0 /cs dqs /dqs dm dq0 i/o 0 dq1 i/o 1 dq2 i/o 2 dq3 i/o 3 dq4 i/o 4 dq5 i/o 5 dq6 i/o 6 i/o 7 dq7 /dqs1 dm1 dqs1 d1 /cs dqs /dqs dm dq8 i/o 0 dq9 i/o 1 dq10 i/o 2 dq11 i/o 3 dq12 i/o 4 dq13 i/o 5 dq14 i/o 6 i/o 7 dq15 /dqs2 dm2 dqs2 d2 /cs dqs /dqs dm dq16 i/o 0 dq17 i/o 1 dq18 i/o 2 dq19 i/o 3 dq20 i/o 4 dq21 i/o 5 dq22 i/o 6 i/o 7 dq23 /dqs3 dm3 dqs3 d3 /cs dqs /dqs dm dq24 i/o 0 dq25 i/o 1 dq26 i/o 2 dq27 i/o 3 dq28 i/o 4 dq29 i/o 5 dq30 i/o 6 i/o 7 dq31 /dqs8 dm8 dqs8 d8 /cs dqs /dqs dm cb0 i/o 0 cb1 i/o 1 cb2 i/o 2 cb3 i/o 3 cb4 i/o 4 cb5 i/o 5 cb6 i/o 6 i/o 7 cb7 /dqs4 dm4 dqs4 d4 /cs dqs /dqs dm dq32 i/o 0 dq33 i/o 1 dq34 i/o 2 dq35 i/o 3 dq36 i/o 4 dq37 i/o 5 dq38 i/o 6 i/o 7 dq39 /dqs5 dm5 dqs5 d5 /cs dqs /dqs dm dq40 i/o 0 dq41 i/o 1 dq42 i/o 2 dq43 i/o 3 dq44 i/o 4 dq45 i/o 5 dq46 i/o 6 i/o 7 dq47 /dqs6 dm6 dqs6 d6 /cs dqs /dqs dm dq48 i/o 0 dq49 i/o 1 dq50 i/o 2 dq51 i/o 3 dq52 i/o 4 dq53 i/o 5 dq54 i/o 6 i/o 7 dq55 /dqs7 dm7 dqs7 d7 /cs dqs /dqs dm dq56 i/o 0 dq57 i/o 1 dq58 i/o 2 dq59 i/o 3 dq60 i/o 4 dq61 i/o 5 dq62 i/o 6 i/o 7 dq63 a1 scl sda a0 a1 wp serial pd scl sa0 sa1 sa2 a1 v dd spd v ref v dd /v ddq v ss serial pd do-d8 do-d8 do-d8 ba0-ba1 a0-a13 /ras /cas sdrams d0-7,d8 cke0 /we odt0 sdrams d0-7,d8 sdrams d0-7,d8 sdrams d0-7,d8 sdrams d0-7,d8 sdrams d0-7,d8 sdrams d0-7,d8 notes: 1. dq,dm,dqs,/dqs resistors : 22 ? +/- 5 %. 2. bax,ax,/ras,/cas,/we resistors : 5.1 ? +/- 5 %. clock signal loads ck0, /ck0 ck1, /ck1 3 3 ck2, /ck2 3 clock input sdrams
rev. 1.0 / apr. 2005 8 1 240pin ddr2 sdram unbuffered dimms functional block diagram 1gb(128mbx64) : hymp512u64[p]8 /s0 /dqs0 dm0 dqs0 d0 / dq0 i/ o 0 dq1 i/ o 1 dq2 i/ o 2 dq3 i/ o 3 dq4 i/ o 4 dq5 i/ o 5 dq6 i/ o 6 i/ o 7 dq7 /dqs1 dm1 dqs1 d1 dq8 i/ o 0 dq9 i/ o 1 dq10 i/ o 2 dq11 i/ o 3 dq12 i/ o 4 dq13 i/ o 5 dq14 i/ o 6 i/ o 7 dq15 /dqs2 dm2 dqs2 d2 dq16 i/ o 0 dq17 i/ o 1 dq18 i/ o 2 dq19 i/ o 3 dq20 i/ o 4 dq21 i/ o 5 dq22 i/ o 6 i/ o 7 dq23 /dqs3 dm3 dqs3 d3 dq24 i/ o 0 dq25 i/ o 1 dq26 i/ o 2 dq27 i/ o 3 dq28 i/ o 4 dq29 i/ o 5 dq30 i/ o 6 i/ o 7 dq31 d8 i/ o 0 i/ o 1 i/ o 2 i/ o 3 i/ o 4 i/ o 5 i/ o 6 i/ o 7 d9 i/ o 0 i/ o 1 i/ o 2 i/ o 3 i/ o 4 i/ o 5 i/ o 6 i/ o 7 d10 i/ o 0 i/ o 1 i/ o 2 i/ o 3 i/ o 4 i/ o 5 i/ o 6 i/ o 7 d11 i/ o 0 i/ o 1 i/ o 2 i/ o 3 i/ o 4 i/ o 5 i/ o 6 i/ o 7 d12 i/ o 0 i/ o 1 i/ o 2 i/ o 3 i/ o 4 i/ o 5 i/ o 6 i/ o 7 d15 i/ o 0 i/ o 1 i/ o 2 i/ o 3 i/ o 4 i/ o 5 i/ o 6 i/ o 7 /dqs4 dm4 dqs4 d4 dq32 i/ o 0 dq33 i/ o 1 dq34 i/ o 2 dq35 i/ o 3 dq36 i/ o 4 dq37 i/ o 5 dq38 i/ o 6 i/ o 7 dq39 /dqs5 dm5 dqs5 d5 dq40 i/ o 0 dq41 i/ o 1 dq42 i/ o 2 dq43 i/ o 3 dq44 i/ o 4 dq45 i/ o 5 dq46 i/ o 6 i/ o 7 dq47 /dqs6 dm6 dqs6 d6 dq48 i/ o 0 dq49 i/ o 1 dq50 i/ o 2 dq51 i/ o 3 dq52 i/ o 4 dq53 i/ o 5 dq54 i/ o 6 i/ o 7 dq55 /dqs7 dm7 dqs7 d7 dq56 i/ o 0 dq57 i/ o 1 dq58 i/ o 2 dq59 i/ o 3 dq60 i/ o 4 dq61 i/ o 5 dq62 i/ o 6 i/ o 7 dq63 d14 i/ o 0 i/ o 1 i/ o 2 i/ o 3 i/ o 4 i/ o 5 i/ o 6 i/ o 7 d13 i/ o 0 i/ o 1 i/ o 2 i/ o 3 i/ o 4 i/ o 5 i/ o 6 i/ o 7 /s1 scl sda a0 a1 wp serial pd scl sa0 sa1 sa2 a1 ba0-ba1 a0-a15 /ras /cas sdrams d0-d15 cke0 /we cke1 odt0 odt1 sdrams d0-d15 sdrams d0-d7 sdrams d8-d15 sdrams d0-d15 sdrams d0-d15 sdrams d0-d15 sdrams d0-d7 sdrams d8-d15 /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm notes: 1. dq,dm,dqs,/dqs resistors : 22 ? +/- 5 %. 2. bax,ax,/ras,/cas,/we resistors : 7.5 ? +/- 5 %. 4 6 6 v dd spd v ref v dd /v ddq v ss serial pd do-d15 do-d15 do-d15 clock signal loads ck0, /ck0 ck1, /ck1 4 6 ck2, /ck2 6 clock input sdrams
rev. 1.0 / apr. 2005 9 1 240pin ddr2 sdram unbuffered dimms functional block diagram 1gb(128mbx72) : hymp512u72[p]8 /s0 /dqs0 dm0 dqs0 d0 / cs dqs /dqs dm dq0 i/ o 0 dq1 i/ o 1 dq2 i/ o 2 dq3 i/ o 3 dq4 i/ o 4 dq5 i/ o 5 dq6 i/ o 6 i/ o 7 dq7 /dqs1 dm1 dqs1 d1 / cs dqs /dqs dm dq8 i/ o 0 dq9 i/ o 1 dq10 i/ o 2 dq11 i/ o 3 dq12 i/ o 4 dq13 i/ o 5 dq14 i/ o 6 i/ o 7 dq15 /dqs2 dm2 dqs2 d2 / cs dqs /dqs dq16 i/ o 0 dq17 i/ o 1 dq18 i/ o 2 dq19 i/ o 3 dq20 i/ o 4 dq21 i/ o 5 dq22 i/ o 6 i/ o 7 dq23 /dqs3 dm3 dqs3 d3 / cs dqs /dqs dm dq24 i/ o 0 dq25 i/ o 1 dq26 i/ o 2 dq27 i/ o 3 dq28 i/ o 4 dq29 i/ o 5 dq30 i/ o 6 i/ o 7 dq31 /dqs8 dm8 dqs8 d8 / cs dqs /dqs dm cb0 i/ o 0 cb1 i/ o 1 cb2 i/ o 2 cb3 i/ o 3 cb4 i/ o 4 cb5 i/ o 5 cb6 i/ o 6 i/ o 7 cb7 d9 / cs dqs /dqs dm i/ o 0 i/ o 1 i/ o 2 i/ o 3 i/ o 4 i/ o 5 i/ o 6 i/ o 7 d10 / cs dqs /dqs dm i/ o 0 i/ o 1 i/ o 2 i/ o 3 i/ o 4 i/ o 5 i/ o 6 i/ o 7 d11 / cs dqs /dqs dm i/ o 0 i/ o 1 i/ o 2 i/ o 3 i/ o 4 i/ o 5 i/ o 6 i/ o 7 d12 / cs dqs /dqs dm i/ o 0 i/ o 1 i/ o 2 i/ o 3 i/ o 4 i/ o 5 i/ o 6 i/ o 7 d17 / cs dqs /dqs dm i/ o 0 i/ o 1 i/ o 2 i/ o 3 i/ o 4 i/ o 5 i/ o 6 i/ o 7 d13 / cs dqs /dqs dm i/ o 0 i/ o 1 i/ o 2 i/ o 3 i/ o 4 i/ o 5 i/ o 6 i/ o 7 d16 / cs dqs /dqs dm i/ o 0 i/ o 1 i/ o 2 i/ o 3 i/ o 4 i/ o 5 i/ o 6 i/ o 7 /dqs4 dm4 dqs4 d4 / cs dqs /dqs dm dq32 i/ o 0 dq33 i/ o 1 dq34 i/ o 2 dq35 i/ o 3 dq36 i/ o 4 dq37 i/ o 5 dq38 i/ o 6 i/ o 7 dq39 /dqs5 dm5 dqs5 d5 / cs dqs /dqs dm dq40 i/ o 0 dq41 i/ o 1 dq42 i/ o 2 dq43 i/ o 3 dq44 i/ o 4 dq45 i/ o 5 dq46 i/ o 6 i/ o 7 dq47 /dqs6 dm6 dqs6 d6 / cs dqs /dqs dm dq48 i/ o 0 dq49 i/ o 1 dq50 i/ o 2 dq51 i/ o 3 dq52 i/ o 4 dq53 i/ o 5 dq54 i/ o 6 i/ o 7 dq55 /dqs7 dm7 dqs7 d7 / cs dqs /dqs dm dq56 i/ o 0 dq57 i/ o 1 dq58 i/ o 2 dq59 i/ o 3 dq60 i/ o 4 dq61 i/ o 5 dq62 i/ o 6 i/ o 7 dq63 d15 / cs dqs /dqs dm i/ o 0 i/ o 1 i/ o 2 i/ o 3 i/ o 4 i/ o 5 i/ o 6 i/ o 7 d14 / cs dqs /dqs dm i/ o 0 i/ o 1 i/ o 2 i/ o 3 i/ o 4 i/ o 5 i/ o 6 i/ o 7 /s1 scl sda a0 a1 wp serial pd scl sa0 sa1 sa2 a1 ba0-ba1 a0-a13 /ras /cas sdrams d0-d17 cke0 /we cke1 odt0 odt1 sdrams d0-d17 sdrams d0-d8 sdrams d9-d17 sdrams d0-d17 sdrams d0-d17 sdrams d0-d17 sdrams d0-d8 sdrams d9-d17 notes: 1. dq,dm,dqs,/dqs resistors : 22 ? +/- 5 %. 2. bax,ax,/ras,/cas,/we resistors : 7.5 ? +/- 5 %. v dd spd v ref v dd /v ddq v ss serial pd do-d17 do-d17 do-d17 clock signal loads ck0, /ck0 ck1, /ck1 6 6 ck2, /ck2 6 clock input sdrams
rev. 1.0 / apr. 2005 10 1 240pin ddr2 sdram unbuffered dimms absolute maximum ratings notes : 1. stress greater than those listed may cause permanent damage to the device. this is a stress rating only, and device functional op eration at or above the conditions indicated is not implied. expousure to absolute maximum rating conditions for extended periods may affect reliablility. operating conditions note : 1. up to 9850 ft. 2. if the dram case temperature is above 85 o c, the auto-refresh command interval has to be reduced to trefi=3.9us. for measurement conditions of t case , please refer to the jedec document jesd51-2. dc operating conditions (sstl_1.8) note : 1. v ddq must be less than or equal to v dd . 2. peak to peak ac noise on v ref may not exeed +/-2% v ref (dc) 3. vtt of transmitting device must track vref of receiving device. parameter symbol value unit note voltage on v dd pin relative to vss v dd - 1.0 v ~ 2.3 v v 1 voltage on v ddl pin relative to vss v ddl - 0.5 v ~ 2.3 v v 1 voltage on v ddq pin relative to vss v ddq - 0.5 v ~ 2.3 v v 1 voltage on any pin relative to vss v in, v out - 0.5 v ~ 2.3 v v 1 storage temperature t stg -50 ~ +100 o c 1 storage humidity(without condensation) h stg 5 to 95 % 1 parameter symbol rating units notes dimm operating temperature(ambient) t opr 0 ~ +55 o c dimm barometric pressure(operating & storage) p bar 105 to 69 k pascal 1 dram component case temperature range t case 0 ~+95 o c 2 parameter symbol min max unit note power supply voltage v dd 1.7 1.9 v v ddl 1.7 1.9 v v ddq 1.7 1.9 v 1 input reference voltage v ref 0.49 x v ddq 0.51 x v ddq v2 eeprom supply voltage v ddspd 1.7 3.6 v termination voltage v tt v ref -0.04 v ref +0.04 v 3
rev. 1.0 / apr. 2005 11 1 240pin ddr2 sdram unbuffered dimms input dc logic level input ac logic level ac input test conditions notes : 1. input waveform timing is referenced to the input signal crossing through the v ref level applied to the device under test. 2. the input signal minimum slew rate is to be maintained over the range from v ref to v ih(ac) min for rising edges and the range from v ref to v il(ac) max for falling edges as shown in the below figure. 3. ac timings are referenced with input waveforms switchin g from vil(ac) to vih(ac) on the positive transitions and vih(ac) to vil(ac) on the negative transitions. parameter symbol min max unit note input high voltage v ih (dc) v ref + 0.125 v ddq + 0.3 v input low voltage v il (dc) -0.30 v ref - 0.125 v parameter symbol min max unit note ac input logic high v ih (ac) v ref + 0.250 - v ac input logic low v il (ac) -v ref - 0.250 v symbol condition value units notes v ref input reference voltage 0.5 * v ddq v1 v swing(max) input signal maximum peak to peak swing 1.0 v 1 slew input signal minimum slew rate 1.0 v/ns 2, 3 v ddq v ih(ac) min v ih(dc) min v ref v il(dc) max v il(ac) max v ss v swing(max) delta tr delta tf v ref - v il (ac) max delta tf falling slew = rising slew = v ih (ac) min - v ref delta tr < figure : ac input test signal waveform>
rev. 1.0 / apr. 2005 12 1 240pin ddr2 sdram unbuffered dimms differential input ac logic level 1. v in (dc) specifies the allowable dc execution of ea ch input of differential pair such as ck, ck , dqs, dqs , ldqs, ldqs , udqs and udqs . 2. v id (dc) specifies the input differential voltage |v tr -v cp | required for switching, where v tr is the true input (such as ck, dqs, ldqs or udqs) level and v cp is the complementary input (such as ck , dqs , ldqs or udqs ) level. the minimum value is equal to v ih (dc) - v il (dc). notes : 1. v id (ac) specifies the input differential voltage |v tr -v cp | required for switching, where v tr is the true input signal (such as ck, dqs, ldqs or udqs) and v cp is the complementary input signal (such as ck , dqs , ldqs or udqs ). the minimum value is equal to v ih (ac) - v il (ac). 2. the typical value of v ix (ac) is expected to be about 0.5 * v ddq of the transmitting device and v ix (ac) is expected to track variations in v ddq . v ix (ac) indicates the voltage at whitch differential input signals must cross. differential ac output parameters notes: 1. the typical value of v ox (ac) is expected to be about 0.5 * v ddq of the transmitting device and v ox (ac) is expected to track variations in v ddq . v ox (ac) indicates the voltage at whitch differential output signals must cross. symbol parameter min. max. units note v id (ac) ac differential input voltage 0.5 v ddq + 0.6 v 1 v ix (ac) ac differential cross point voltage 0.5 * v ddq - 0.175 0.5 * v ddq + 0.175 v 2 symbol parameter min. max. units note v ox (ac) ac differential cross point voltage 0.5 * v ddq - 0.125 0.5 * v ddq + 0.125 v 1 v ddq crossing point v ssq v tr v cp v id v ix or v ox < differential signal levels >
rev. 1.0 / apr. 2005 13 1 240pin ddr2 sdram unbuffered dimms output buffer levels output ac test conditions notes: 1. the vddq of the device under test is referenced. output dc current drive notes: 1. v ddq = 1.7 v; v out = 1420 mv. (v out - v ddq )/i oh must be less than 21 ohm for values of v out between v ddq and v ddq - 280 mv. 2. v ddq = 1.7 v; v out = 280 mv. v out /i ol must be less than 21 ohm for values of v out between 0 v and 280 mv. 3. the dc value of v ref applied to the receiving device is set to v tt 4. the values of i oh (dc) and i ol (dc) are based on the conditions given in notes 1 and 2. they are used to test device drive current capability to ensure v ih min plus a noise margin and v il max minus a noise margin are delivered to an sstl_18 receiver. the actual current values are derived by shifting the desired driver operating po int along a 21 ohm load line to define a convenient driver current for measurement. symbol parameter sstl_18 units notes v otr output timing measurement reference level 0.5 * v ddq v1 symbol parameter sstl_18 units notes i oh(dc) output minimum source dc current - 13.4 ma 1, 3, 4 i ol(dc) output minimum sink dc current 13.4 ma 2, 3, 4
rev. 1.0 / apr. 2005 14 1 240pin ddr2 sdram unbuffered dimms pin capacitance (vdd=1.8v,vddq=1.8v, ta=25 . f=1mhz ) 256mb : hymp532u64[p]6 512mb : hymp564u64[p]8 512mb : hymp564u72[p]8 1gb : hymp512u64[p]8 1gb : hymp512u72[p]8 notes: 1. pins not under test are tied to gnd. 2. these value are guaranteed by design and tested on a sample basis only. pin symbol min max unit ck, ck cck 18 22 pf cke, odt,cs ci1 57 63 pf address, ras , cas , we ci2 42 48 pf dq, dm, dqs, dqs cio 7 9 pf pin symbol min max unit ck, ck cck 22 30 pf cke, odt,cs ci1 62 84 pf address, ras , cas , we ci2 42 64 pf dq, dm, dqs, dqs cio 6 9 pf pin symbol min max unit ck, ck cck 22 30 pf cke, odt,cs ci1 63 85 pf address, ras , cas , we ci2 43 66 pf dq, dm, dqs, dqs cio 6 9 pf pin symbol min max unit ck, ck cck 22 35 pf cke, odt,cs ci1 64 87 pf address, ras , cas , we ci2 50 88 pf dq, dm, dqs, dqs cio 8 13 pf pin symbol min max unit ck, ck cck 23 35 pf cke, odt,cs ci1 65 89 pf address, ras , cas , we ci2 52 92 pf dq, dm, dqs, dqs cio 9 13 pf
rev. 1.0 / apr. 2005 15 1 240pin ddr2 sdram unbuffered dimms idd specifications (t case : 0 to 95 o c) 256mb, 32m x 64 u-dimm : hymp532u64[p]6 512mb, 64m x 64 u - dimm : hymp564u64[p]8 notes: 1. idd6 current values are guaranted up to tcase of 85 max. symbol e3(ddr2 400@cl 3) c4(ddr2 533@cl 4) unit note idd0 500 520 ma idd1 540 560 ma idd2p 24 28 ma idd2q 140 160 ma idd2n 160 180 ma idd3p(f) 80 100 ma idd3p(s) 20 24 ma idd3n 260 300 ma idd4w 720 880 ma idd4r 600 760 ma idd5b 660 700 ma idd6 22 22 ma 1 idd7 1320 1320 ma symbol e3(ddr2 400@cl3) c4(ddr2 533@cl 4) unit note idd0 640 720 ma idd1 720 800 ma idd2p 48 56 ma idd2q 280 320 ma idd2n 320 360 ma idd3p(f) 160 200 ma idd3p(s) 40 48 ma idd3n 440 520 ma idd4w 1200 1440 ma idd4r 1040 1280 ma idd5b 1320 1400 ma idd6 44 44 ma 1 idd7 1760 1760 ma
rev. 1.0 / apr. 2005 16 1 240pin ddr2 sdram unbuffered dimms 512mb, 64m x 72 ecc u - dimm : hymp564u72[p]8 1gb, 128m x 64 u - dimm : hymp512u64[p]8 notes: 1. idd6 current values are guaranted up to tcase of 85 max. symbol e3(ddr2 400@cl 3) c4(ddr2 533@cl 4) unit note idd0 720 810 ma idd1 810 900 ma idd2p 54 63 ma idd2q 315 360 ma idd2n 360 405 ma idd3p(f) 180 225 ma idd3p(s) 45 54 ma idd3n 495 585 ma idd4w 1350 1620 ma idd4r 1170 1440 ma idd5b 1485 1575 ma idd6 50 50 ma 1 idd7 1980 1980 ma symbol e3(ddr2 400@cl 3) c4(ddr2 533@cl 4) unit note idd0 1080 1240 ma idd1 1160 1320 ma idd2p 96 112 ma idd2q 560 640 ma idd2n 640 720 ma idd3p(f) 320 400 ma idd3p(s) 80 96 ma idd3n 880 1040 ma idd4w 1640 1960 ma idd4r 1480 1800 ma idd5b 1760 1920 ma idd6 88 88 ma 1 idd7 2200 2280 ma
rev. 1.0 / apr. 2005 17 1 240pin ddr2 sdram unbuffered dimms 1gb, 128m x 72 ecc u - dimm : hymp512u72[p]8 notes: 1. idd6 current values are guaranted up to tcase of 85 max. symbol e3(ddr2 400@cl 3) c4(ddr2 533@cl 4) unit note idd0 1215 1395 ma idd1 1305 1485 ma idd2p 108 126 ma idd2q 630 720 ma idd2n 720 810 ma idd3p(f) 360 450 ma idd3p(s) 90 108 ma idd3n 990 1170 ma idd4w 1845 2205 ma idd4r 1665 2025 ma idd5b 1980 2160 ma idd6 99 99 ma 1 idd7 2475 2565 ma
rev. 1.0 / apr. 2005 18 1 240pin ddr2 sdram unbuffered dimms idd measurement conditions notes: 1. idd specifications are tested after the device is properly initialized 2. input slew rate is specified by ac parametric test condition 3. idd parameters are specified with odt disabled. 4. data bus consists of dq, dm, dqs, dqs , rdqs, rdqs , ldqs, ldqs, udqs, and udqs . idd values must be met with all combinations of emrs bits 10 and 11. 5. definitions for idd low is defined as vin vilac(max) high is defined as vin vihac(min) stable is defined as inputs stable at a high or low level floating is defined as inputs at vref = vddq/2 switching is defined as: inputs changing between high and low every other clock cycle (once per two clocks) for address and control sig nals, and inputs changing between high and low every other data transfer (once per clock) for dq signals not including masks or strobes. symbol conditions units idd0 operating one bank active-precharge current ; t ck = t ck(idd), t rc = t rc(idd), t ras = t rasmin(idd);cke is high, cs is high between valid commands;address bus inputs are switching;data bus inputs are switching ma idd1 operating one bank active-read-precharge curren ; iout = 0ma;bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t rc = t rc (idd), t ras = t rasmin(idd), t rcd = t rcd(idd) ; cke is high, cs is high between valid commands ; address bus inputs are swit ching ; data pattern is same as idd4w ma idd2p precharge power-down current ; all banks idle ; t ck = t ck(idd) ; cke is low ; other control and address bus inputs are stable; data bus inputs are floating ma idd2q precharge quiet standby current ;all banks idle; t ck = t ck(idd);cke is high, cs is high; other control and address bus inputs are stable; data bus inputs are floating ma idd2n precharge standby current ; all banks idle; t ck = t ck(idd); cke is high, cs is high; other control and address bus inputs are switching; data bus inputs are switching ma idd3p active power-down current ; all banks open; t ck = t ck(idd); cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mrs(12) = 0 ma slow pdn exit mrs(12) = 1 ma idd3n active standby current ; all banks open; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching ma idd4w operating burst write current ; all banks open, continuous burst writes; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs is high between valid commands; address bus inputs are switching; data bus inputs are switching ma idd4r operating burst read current ; all banks open, continuous burst reads, iout = 0ma; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs is high between valid com- mands; address bus inputs are switching;; data pattern is same as idd4w ma idd5b burst refresh current ; t ck = t ck(idd); refresh command at every t rfc(idd) interval; cke is high, cs is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching ma idd6 self refresh current ; ck and ck at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating. idd6 current values are guaranted up to tcase of 85 max. normal ma low power idd7 operating bank interleave read current ; all bank interleaving reads, iout = 0ma; bl = 4, cl = cl(idd), al = t rcd(idd)-1* t ck(idd); t ck = t ck(idd), t rc = t rc(idd), t rrd = t rrd(idd), t rcd = 1* t ck(idd); cke is high, cs is high between valid commands; address bus inputs are stable during deselects; data pattern is same as idd4r; - refer to the fo llowing page for detailed timing conditions ma
rev. 1.0 / apr. 2005 19 1 240pin ddr2 sdram unbuffered dimms electrical characteri stics & ac timings speed bins and cl,trcd,trp,trc and tras for corresponding bin ac timing parameters by speed grade speed ddr2-533 (c4) ddr2-400 (e3) unit bin(cl-trcd-trp) 4-4-4 3-3-3 parameter min min cas latency 4 3 tck trcd 15 15 ns trp 15 15 ns trc 60 55 ns tras 45 40 ns parameter symbol ddr2-400 ddr2-533 unit note min max min max data-out edge to clock edge skew tac -600 600 -500 500 ps dqs-out edge to clock edge skew tdqsck -500 500 -450 450 ns clock high level width tch 0.45 0.55 0.45 0.55 ck clock low level width tcl 0.45 0.55 0.45 0.55 ck clock half period thp min (tcl,tch) - min (tcl,tch) -ns system clock cycle time tck 5000 8000 3750 8000 ps dq and dm input setup time tds 150 - 100 - ps 1 dq and dm input hold time tdh 275 - 225 - ps 1 dq and dm input setup time(single-ended strobe) tds1 25 - -25 - ps 1 dq and dm input hold time(sin gle-ended strobe) tdh1 25 - -25 - ps 1 control & address input pulse width for each input tipw 0.6 - 0.6 - tck dq and dm input pulse witd th for each input pulse width for each input tdipw 0.35 - 0.35 - tck data-out high-impedance window from ck, /ck thz - tac max - tac max ps dqs low-impedance time from ck/ck tlz(dqs) tac min tac max tac min tac max ps dq low-impedance time from ck/ck tlz(dq) 2*tac min tac max 2*tac min tac max ps dqs-dq skew for dqs and associated dq signals tdqsq - 350 -300 ps dq hold skew factor tqhs - 450 -400 ps dq/dqs output hold time from dqs tqh thp - tqhs - thp - tqhs - ps first dqs latching transition to associated clock edge tdqss -0.25 +0.25 -0.25 +0.25 tck dqs input high pulse width tdqsh 0.35 - 0.35 - tck dqs input low pulse width tdqsl 0.35 - 0.35 - tck dqs falling edge to ck setup time tdss 0.2 - 0.2 - tck dqs falling edge hold time from ck tdsh 0.2 - 0.2 - tck mode register set command cycle time tmrd 2 - 2 - tck write postamble twpst 0.4 0.6 0.4 0.6 tck write preamble twpre 0.35 - 0.35 - tck
rev. 1.0 / apr. 2005 20 1 240pin ddr2 sdram unbuffered dimms - continued - notes : 1. for details and notes, please refer to the rele vant hynix component data sheet(hy5ps12[8/16]21(l)f). 2. 0 c g tcase g 85 c 3. 85 c xg tcase gg 95 c parameter symbol ddr2-400 ddr2-533 unit note min max min max address and control input setup time tis 350 -250 - ps address and control input hold time tih 475 -375 - ps read preamble trpre 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 tck auto-refresh to active /auto-refresh command period trfc 105 - 105 - ns row active to row active delay for 1kb page size trrd 7.5 - 7.5 - ns row active to row active delay for 2kb page size trrd 10 - 10 - ns four activate window for 1kb page size tfaw 37.5 - 37.5 - ns four activate window for 2kb page size tfaw 50 - 50 - ns cas to cas command delay tccd 2 2 tck write recovery time twr 15 -15 - ns auto precharge write recovery + precharge time tdal twr+trp - twr+trp - tck write to read command delay twtr 10 - 7.5 - ns internal read to precharge command delay trtp 7.5 7.5 ns exit self refresh to a non-read command txsnr trfc + 10 trfc + 10 ns exit self refresh to a read command txsrd 200 - 200 - tck exit precharge power down to any non-read command txp 2 - 2 - tck exit active power down to read command txard 2 2 tck exit active power down to read command (slow exit, lower power) txards 6 - al 6 - al tck cke minimum pulse width(high and low pulse width) t cke 3 3 tck odt turn-on delay t aond 2222tck odt turn-on t aon tac(min) tac(max) +1 tac(min) tac(max) +1 ns odt turn-on(powe r-down mode) t aonpd tac(min)+2 2tck+tac (max)+1 tac(min)+2 2tck+tac (max)+1 ns odt turn-off delay t aofd 2.52.52.52.5tck odt turn-off t aof tac(min) tac(max) + 0.6 tac(min) tac(max) + 0.6 ns odt turn-off (power-down mode) t aofpd tac(min)+2 2.5tck+ta c(max)+1 tac(min)+2 2.5tck+ta c(max)+1 ns odt to power down entry latency tanpd 3 3 tck odt power down exit latency taxpd 8 8 tck ocd drive mode output delay toit 0 12 0 12 ns minimum time clocks remains on after cke asynchronously drops low tdelay tis+tck+tih tis+tck+tih ns average periodic refresh interval trefi - 7.8 - 7.8 us 2 trefi - 3.9 - 3.9 us 3
rev. 1.0 / apr. 2005 21 1 240pin ddr2 sdram unbuffered dimms package outline 32mx64 - hymp532u64[p]6 note) all dimensions are typical millimeter scale unless otherw ise stated. frontside view 30.0 4.00.1 133.35 63.0 5.175 5.175 55.0 5.0 backside view 0.8 0.05 1.0 0.20 detail of contacts a 2.50 0.20 detail of contacts b 2.50 1.50 0.10 3.80 5.00 detail-a detail-b side 3.18 max (front) 1.27 0.10 3.0 3.0 10.0 17.80
rev. 1.0 / apr. 2005 22 1 240pin ddr2 sdram unbuffered dimms package outline 64mx[64/72] - hymp564u[64/72][p]8 front 30.0 4.00.1 133.35 63.0 5.175 5.175 55.0 5.0 back 0.8 0.05 1.0 0.20 detail of contacts a 2.50 0.20 detail of contacts b 2.50 1.50 0.10 3.80 5.00 3.0 3.0 10.0 17.80 detail-a detail-b ecc(x72) only. note) all dimensions are typical millimeter scale unless otherw ise stated. side 2.7 max (front) 1.27 0.10
rev. 1.0 / apr. 2005 23 1 240pin ddr2 sdram unbuffered dimms package outline 128mx[64/72] - hymp512u[64/72][p]8 front 30.0 4.00.1 133.35 63.0 5.175 5.175 55.0 5.0 back 0.8 0.05 1.0 0.20 detail of contacts a 2.50 0.20 detail of contacts b 2.50 1.50 0.10 3.80 5.00 side 4.00 max. 1.27 0.10 3.0 3.0 10.0 17.80 detail-a detail-b ecc(x72) only. ecc(x72) only. note) all dimensions are typical millimeter scale unless otherw ise stated.
rev. 1.0 / apr. 2005 24 1 240pin ddr2 sdram unbuffered dimms revision history revision history date remark 1.0 first version release - data sheet coverage is changed from an individual module part to a component based module family. feb. 2005 added v ddl spec, corrected tds & tdh spec values. apr. 2005

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